36.9.2 DSM Control Register 1
Note:
- Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
| Name: | MDxCON1 |
| Offset: | 0x6B |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHPOL | CHSYNC | CLPOL | CLSYNC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 5 – CHPOL DSM High Carrier Polarity Select
| Value | Description |
|---|---|
| 1 | Selected high carrier signal is inverted |
| 0 | Selected high carrier signal is not inverted |
Bit 4 – CHSYNC DSM High Carrier Synchronization Enable
| Value | Description |
|---|---|
| 1 | DSM waits for a falling edge on the high carrier signal before allowing a switch to the low carrier signal |
| 0 | DSM output is not synchronized to the high carrier signal(1) |
Bit 1 – CLPOL DSM Low Carrier Polarity Select
| Value | Description |
|---|---|
| 1 | Selected low carrier signal is inverted |
| 0 | Selected low carrier signal is not inverted |
Bit 0 – CLSYNC DSM Low Carrier Synchronization Enable
| Value | Description |
|---|---|
| 1 | DSM waits for a falling edge on the low carrier signal before allowing a switch to the high carrier signal |
| 0 | DSM output is not synchronized to the low carrier signal(1) |