14.6.5.1.4 Loop Divider Ratio Updates

The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register only when the GCLK_DPLL_32K (GCLK.PCHCTRL1) is configured and enabled. The FDPLL reference clock (DPLLCTRLB.REFCLK) can still be set to one of the three options (XOSC, XOSC32K, GCLK) as long as GCLK_DPLL_32K is active.

STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell has successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state.