38.7.12 Comparator Control n

Name: COMPCTRL
Offset: 0x10 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized

Bit 3130292827262524 
   OUT[1:0] FLEN[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
     HYSTEN SPEED[1:0] 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
 SWAPMUXPOS[2:0] MUXNEG[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
  RUNSTDBY INTSEL[1:0]SINGLEENABLE  
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 29:28 – OUT[1:0] Output

These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero.

Note: For internal use of the comparison results by the CCL, this bit must be 0x1 or 0x2.

These bits are not synchronized.

ValueNameDescription
0x0 OFF The output of COMPn is not routed to the COMPn I/O port
0x1 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port
0x2 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
0x3 N/A Reserved

Bits 26:24 – FLEN[2:0] Filter Length

These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueNameDescription
0x0 OFF No filtering
0x1 MAJ3 3-bit majority function (2 of 3)
0x2 MAJ5 5-bit majority function (3 of 5)
0x3-0x7 N/A Reserved

Bit 19 – HYSTEN Hysteresis Enable

This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0).

This bit is not synchronized.

ValueDescription
0 Hysteresis is disabled.
1 Hysteresis is enabled.

Bits 17:16 – SPEED[1:0] Speed Selection

This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

Value Name Description
0x0 LOW Low speed
0x3 HIGH High speed

Bit 15 – SWAP Swap Inputs and Invert

This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueDescription
0 The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input.
1 The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input.

Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection

These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueNameDescription
0x0 PIN0 I/O pin 0
0x1 PIN1 I/O pin 1
0x2 PIN2 I/O pin 2
0x3 PIN3 I/O pin 3
0x4 VSCALE VDD scaler
0x5–0x7 Reserved

Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection

These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueNameDescription
0x0 PIN0 I/O pin 0
0x1 PIN1 I/O pin 1
0x2 PIN2 I/O pin 2
0x3 PIN3 I/O pin 3
0x4 GND Ground
0x5 VSCALE VDD scaler
0x6 INTREF Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL for voltage level information)
0x7 DAC DAC output

Bit 6 – RUNSTDBY Run in Standby

This bit controls the behavior of the comparator during standby sleep mode.

This bit is not synchronized

ValueDescription
0 The comparator is disabled during sleep.
1 The comparator continues to operate during sleep.

Bits 4:3 – INTSEL[1:0] Interrupt Selection

These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueNameDescription
0x0 TOGGLE Interrupt on comparator output toggle
0x1 RISING Interrupt on comparator output rising
0x2 FALLING Interrupt on comparator output falling
0x3 EOC Interrupt on end of comparison (single-shot mode only)

Bit 2 – SINGLE Single-Shot Mode

This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero.

These bits are not synchronized.

ValueDescription
0 Comparator n operates in continuous measurement mode.
1 Comparator n operates in single-shot mode.

Bit 1 – ENABLE Enable

Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n.

Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set. SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.

Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.