39.7.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized Bits |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | SWRST | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
Note: This bit is not synchronized
| Value | Description |
|---|---|
| 0 | The DAC output buffer is disabled in standby sleep mode. |
| 1 | The DAC output buffer can be enabled in standby sleep mode. |
Bit 1 – ENABLE Enable DAC Controller
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the
CTRLA.ENABLE synchronization is complete.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled or being disabled. |
| 1 | The peripheral is enabled or being enabled. |
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the DAC to their initial state, and the DAC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the
CTRLA.SWRST synchronization is complete.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |