39.7.8 Data DAC

Note: This register is write-synchronized: SYNCBUSY.DATA must be checked to ensure the DATA register synchronization is complete.
Name: DATA
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized

Bit 15141312111098 
 DATA[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 DATA[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bits 15:0 – DATA[15:0] Data value to be converted

DATA register contains the 10-bit value that is converted to a voltage by the DAC. The adjustment of these 10 bits within the 16-bit register is controlled by CTRLB.LEFTADJ.

Four additional bits are also used for the dithering feature according to 39.6.8.4 Dithering mode.

Table 39-1. Valid Data Bits
CTRLB.DITHER CTRLB.LEFTADJ DATA Description
0 0 DATA[9:0] Right adjusted, 10-bits
0 1 DATA[15:6] Left adjusted, 10-bits
1 0 DATA[13:4], DATA[3:0] Right adjusted, 14-bits
1 1 DATA[15:6], DATA[5:2] Left adjusted, 14-bits