34.6.3.3 Dithering Operation

The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. The TCC does not support dithering with any RAMP2 operation.

Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns. The use of dithering with an external retrigger event (EVCTRL.EVACTx) is not possible as the event can lead to unexpected stretch of right aligned pulses, or shrinking of left aligned pulses.

Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register (CTRLA.RESOLUTION):

DITH4 enable dithering every 16 PWM frames
DITH5 enable dithering every 32 PWM frames
DITH6 enable dithering every 64 PWM frames

The DITHERCY bits of COUNT, PER and CCx define the dithercy increment value and so the number of extra cycles to add into the frame (DITHERCY bits from the respective COUNT, PER or CCx registers). The remaining bits of COUNT, PER, CCx define the compare value itself.

The pseudo code, giving the extra cycles insertion regarding the cycle is:

int extra_cycle(resolution, dithercy, cycle){
  int MASK;
  int value
  switch (resolution){
    DITH4: MASK = 0x0f;
    DITH5: MASK = 0x1f;
    DITH6: MASK = 0x3f;
  }
  value = cycle * dithercy;
  if (((MASK & value) + dithercy) > MASK)
    return 1;
 return 0;
}

Dithering on Period

Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.

DITH4 mode:

P w m P e r i o d = (\frac{DITHERCY}{16} + PER) (\frac{1}{f_{GCLK_TCC}})

Note: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx register correspond to the DITHERCY value (the last 4 significant bits from COUNT are always read as 0), rest of the bits corresponds to PER/CCx or COUNT value.

DITH5 mode: