35.6.2.1 Initialization

The CCL bus clock (CLK_CCL_APB) is required to access the CCL registers. This clock can be enabled in the MCLK - Main Clock module.

A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the GCLK - Generic Clock Controller before using input events, filter, edge detection or sequential logic.

The following bits are enable-protected, meaning that they can only be written when the CCL module is disabled (CTRL.ENABLE=0):

• Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register
• LUT Control n (LUTCTRLn) register, except the ENABLE bit

Enable-protected bits in the LUTCTRLn registers can be written at the same time as LUTCTRLn.ENABLE is written to '1', but not at the same time as LUTCTRLn.ENABLE is written to '0'.

Enable-protection is denoted by the Enable-Protected property in the register description.