35.6.2.2 Enabling, Disabling, and Resetting

The CCL is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The CCL is disabled by writing a '0' to CTRL.ENABLE. When using sequential logic the control register enable must be written twice when enabling (CTRL.ENABLE = 1).

Each LUT is enabled by writing a '1' to the Enable bit in the LUT Control n register (LUTCTRLn.ENABLE). Each LUT is disabled by writing a '0' to LUTCTRLn.ENABLE.

The CCL is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the CCL will be reset to their initial state, and the CCL will be disabled. Refer to CTRL35.7.1 Control for details.

When the Peripheral Access Controller (PAC) is enabled for the CCL module (WRCTRL.PERID = 87) and a Software Reset (CTRL.SWRST) is executed, a PAC protection error will be generated. If the PAC interrupt is enabled, the interrupt flag for the CCL module (INTFLAGC.CCL) should be cleared.