21.6.1 Control A
Note: This register is write-protected while DIVAS is busy. Accesses while protected
will result in an error.
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DLZ | SIGNED | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DLZ Disable Leading Zero Optimization
| Value | Description |
|---|---|
| 0 | Enable leading zero optimization; 32-bit division takes 2-16 cycles. |
| 1 | Disable leading zero optimization; 32-bit division takes 16 cycles. |
Bit 0 – SIGNED Signed Division Enable
| Value | Description |
|---|---|
| 0 | Unsigned division. |
| 1 | Signed division. |