14.7.15 DPLL Prescaler

Note: DPLLPRESC is a write-synchronized register: DPLLSYNCBUSY.DPLLPRESC must be checked to ensure the DPLLPRESC synchronization is complete.
Name: DPLLPRESC
Offset: 0x28
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 76543210 
       PRESC[1:0] 
Access R/WR/W 
Reset 00 

Bits 1:0 – PRESC[1:0] Output Clock Prescaler

These bits define the output clock prescaler setting.

ValueNameDescription
0x0 DIV1 DPLL output is divided by 1
0x1 DIV2 DPLL output is divided by 2
0x2 DIV4 DPLL output is divided by 4
0x3 Reserved