14.7.13 DPLL Ratio Control

Note: DPLLRATIO is a write-synchronized register: DPLLSYNCBUSY.DPLLRATIO must be checked to ensure the DPLLRATIO synchronization is complete.
Name: DPLLRATIO
Offset: 0x20
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     LDRFRAC[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
     LDR[11:8] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 LDR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part

Writing these bits selects the fractional part of the frequency multiplier.

Bits 11:0 – LDR[11:0] Loop Divider Ratio

Writing these bits selects the integer part of the frequency multiplier.