35.7.3 LUT Control n
Note: The LUTCTRLn register is Enable
Protected when CCL.CTRL.ENABLE = 1.
| Name: | LUTCTRLn |
| Offset: | 0x08 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRUTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LUTEO | LUTEI | INVEI | INSEL2[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INSEL1[3:0] | INSEL0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EDGESEL | FILTSEL[1:0] | ENABLE | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:24 – TRUTH[7:0] Truth Table
These bits define the value of truth logic as a function of inputs IN[2:0].
Bit 22 – LUTEO LUT Event Output Enable
| Value | Description |
|---|---|
| 0 | LUT event output is disabled. |
| 1 | LUT event output is enabled. |
Bit 21 – LUTEI LUT Event Input Enable
| Value | Description |
|---|---|
| 0 | LUT incoming event is disabled. |
| 1 | LUT incoming event is enabled. |
Bit 20 – INVEI Inverted Event Input Enable
| Value | Description |
|---|---|
| 0 | Incoming event is not inverted. |
| 1 | Incoming event is inverted. |
Bits 8:11, 12:15, 16:19 – INSELx LUT Input x Source Selection
These bits select the LUT input x source:
| Value | Name | Description |
|---|---|---|
| 0x0 | MASK | Masked input |
| 0x1 | FEEDBACK | Feedback input source |
| 0x2 | LINK | Linked LUT input source |
| 0x3 | EVENT | Event input source |
| 0x4 | IO | I/O pin input source |
| 0x5 | AC | AC input source: CMP[0] (LUT0) / CMP[1] (LUT1) |
| 0x6 | TC | TC input source: TC0 (LUT0) / TC1 (LUT1)/ TC2 (LUT2) / TC3 (LUT3) |
| 0x7 | ALTTC | Alternative TC input source: TC1 (LUT0) / TC2 (LUT1) / TC3 (LUT2) / TC4 (LUT3) |
| 0x8 | TCC | TCC input source: TCC0 (LUT0) / TCC1 (LUT1)/ TCC2 (LUT2) |
| 0x9 | SERCOM | SERCOM input source: SERCOM0 (LUT0) / SERCOM1 (LUT1)/ SERCOM2 (LUT2) / SERCOM3 (LUT3) |
| 0xA - 0xF | Reserved | Reserved |
Bit 7 – EDGESEL Edge Selection
| Value | Description |
|---|---|
| 0 | Edge detector is disabled. |
| 1 | Edge detector is enabled. |
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Filter disabled |
| 0x1 | SYNCH | Synchronizer enabled |
| 0x2 | FILTER | Filter enabled |
| 0x3 | - | Reserved |
Bit 1 – ENABLE LUT Enable
| Value | Description |
|---|---|
| 0 | The LUT is disabled. |
| 1 | The LUT is enabled. |