35.7.2 Sequential Control x

Note: The SEQCTRL0 (SEQCTRL1) register is Enable-protected when CCL.CTRL.ENABLE = 1.
Name: SEQCTRL
Offset: 0x04 + n*0x01 [n=0..1]
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected

Bit 76543210 
     SEQSEL[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:0 – SEQSEL[3:0] Sequential Selection

These bits select the sequential configuration:

Sequential Selection

ValueNameDescription
0x0 DISABLE Sequential logic is disabled
0x1 DFF D flip flop
0x2 JK JK flip flop
0x3 LATCH D latch
0x4 RS RS latch
0x5 - 0xF Reserved