35.7.1 Control

Note: CTRL register (except the bits ENABLE & SWRST) is Enable Protected when CCL.CTRL.ENABLE = 1.
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
  RUNSTDBY    ENABLESWRST 
Access R/WR/WW 
Reset 000 

Bit 6 – RUNSTDBY Run in Standby

This bit indicates if the GCLK_CCL clock must be kept running in standby mode. The setting is ignored for configurations where the generic clock is not required. For details refer to 35.6.4 Sleep Mode Operation.

Important: This bit must be written before enabling the CCL.
ValueDescription
0 Generic clock is not required in standby sleep mode.
1 Generic clock is required in standby sleep mode.

Bit 1 – ENABLE Enable

ValueDescription
0 The peripheral is disabled.
1 The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the CCL to their initial state.

ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.