42.7.15 Counter Value
Note: This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the
COUNT register synchronization is complete.
Name: | COUNT |
Offset: | 0x1C |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Read-Synchronized, Write-Synchronized |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
COUNT[15:8] | |||||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
COUNT[7:0] | |||||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:0 – COUNT[15:0] Counter Value
These bits contain the counter value. To read the most updated counter value, the READSYNC software command must be applied first (CTRLBSET.CMD = READSYNC).