21.9 Asynchronous Operation of Timer/Counter2

When TC2 operates asynchronously, some considerations must be taken:

  • When switching between asynchronous and synchronous clocking of TC2, the registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is:
    1. Disable the TC2 interrupts by clearing OCIE2x and TOIE2.
    2. Select clock source by setting AS2 as appropriate.
    3. Write new values to TCNT2, OCR2x, and TCCR2x.
    4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
    5. Clear the TC2 interrupt flags.
    6. Enable interrupts, if needed.
  • The CPU main clock frequency must be more than four times the oscillator frequency.
  • When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers has its individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. The Asynchronous Status Register (ASSR) indicates that a transfer to the destination register has taken place.
  • When entering Power-Save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if TC2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupts is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up.
  • If TC2 is used to wake the device up from Power-Save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within the TOSC1 cycle, the interrupt will immediately occur and the device wakes up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
    1. Write a value to TCCR2x, TCNT2, or OCR2x.
    2. Wait until the corresponding update busy flag in ASSR returns to zero.
    3. Enter Power-Save or ADC Noise Reduction mode.
  • When the asynchronous operation is selected, the 32.768 kHz oscillator for TC2 is always running, except in Power-Down and Standby modes. After a Power-up Reset or wake-up from Power-Down or Standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using TC2 after power-up or wake-up from Power-Down or Standby mode. The contents of all TC2 registers must be considered lost after a wake-up from Power-Down or Standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the TOSC1 pin.
  • Description of wake up from Power-Save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
  • Reading of the TCNT2 register shortly after wake-up from Power-Save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-Save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-Save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
    1. Wait for the corresponding update busy flag to be cleared.
    2. Read TCNT2.
  • During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock.