21.8 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 21-8. Timer/Counter Timing Diagram, no Prescaling

The following figure shows the same timing data, but with the prescaler enabled.

Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

The following figure shows the setting of OCF2A in all modes except CTC mode.

Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)

The following figure shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 21-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)