10.6.6 GPIOR1 – General Purpose I/O Register 1
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
| Name: | GPIOR1 |
| Offset: | 0x4A |
| Reset: | 0x00 |
| Property: | When addressing as I/O Register: address offset is 0x2A |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GPIOR1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |