9.5.1 Stack Pointer Register Low and High byte
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
| Name: | SPL and SPH |
| Offset: | 0x5D |
| Reset: | 0x4FF |
| Property: | When addressing I/O Registers as data space the offset address is 0x3D |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SP11 | SP10 | SP9 | SP8 | ||||||
| Access | R | R | R | R | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SP7 | SP6 | SP5 | SP4 | SP3 | SP2 | SP1 | SP0 | ||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – SP Stack Pointer Register
SPL and SPH are combined into SP.