19.3 Accessing 16-bit Timer/Counter Registers

The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be accessed byte-wise, using two read or write operations. Each 16-bit timer has a single 8-bit TEMP register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer.

Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently.

Note: To perform a 16-bit write operation, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.

Not all 16-bit accesses use the temporary register for the high byte. Reading the OCRnA/B 16-bit registers does not involve using the temporary register.

16-bit Access

The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B and ICRn registers. Note that when using C, the compiler handles the 16-bit access.

Assembly Code Example(1)

   ...
; Set TCNTn to 0x01FF
ldi    r17,0x01
ldi    r16,0xFF
out    TCNTnH,r17
out    TCNTnL,r16
; Read TCNTn into r17:r16
in    r16,TCNTnL
in    r17,TCNTnH
   ...

The assembly code example returns the TCNTn value in the r17:r16 register pair.

C Code Example(1)

unsigned int i;
   ...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
   ...
Note:
  1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

Atomic Read

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.

The following code examples show how to perform an atomic read of the TCNTn register contents. The OCRnA/B or ICRn registers can be ready by using the same principle.

Assembly Code Example(1)

TIM16_ReadTCNTn:
   ; Save global interrupt flag
   in    r18,SREG
   ; Disable interrupts
   cli
   ; Read TCNTn into r17:r16
   in    r16,TCNTnL
   in    r17,TCNTnH
   ; Restore global interrupt flag
   out   SREG,r18
   ret

The assembly code example returns the TCNTn value in the r17:r16 register pair.

C Code Example(1)

unsigned int TIM16_ReadTCNTn( void )
{
   unsigned char sreg;
   unsigned int i;
   /* Save global interrupt flag */
   sreg = SREG;
   /* Disable interrupts */
   _CLI();
   /* Read TCNTn into i */
   i = TCNTn;
   /* Restore global interrupt flag */
   SREG = sreg;
   return i;
}
Note:
  1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

Atomic Write

The following code examples show how to do an atomic write of the TCNTn register contents. Writing any of the OCRnA/B or ICRn registers can be done by using the same principle.

Assembly Code Example(1)

TIM16_WriteTCNTn:
   ; Save global interrupt flag
   in     r18,SREG
   ; Disable interrupts
   cli
   ; Set TCNTn to r17:r16
   out    TCNTnH,r17
   out    TCNTnL,r16
   ; Restore global interrupt flag
   out    SREG,r18
   ret

The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn.

C Code Example(1)

void TIM16_WriteTCNTn( unsigned int i )
{
   unsigned char sreg;
   unsigned int i;
   /* Save global interrupt flag */
   sreg = SREG;
   /* Disable interrupts */
   _CLI();
   /* Set TCNTn to i */
   TCNTn = i;
   /* Restore global interrupt flag */
   SREG = sreg;
}
Note:
  1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.