24.12.4 USART Control and Status Register n C
| Name: | UCSRC |
| Offset: | 0xC2 + n*0x08 [n=0..1] |
| Reset: | 0x06 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UMSELn[1:0] | UPMn[1:0] | USBSn | UCSZn1 / UDORDn | UCSZn0 / UCPHAn | UCPOLn | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | |
Bits 7:6 – UMSELn[1:0] USART Mode Select
These bits select the mode of operation of the USARTn
| UMSEL[1:0] | Mode |
|---|---|
| 00 | Asynchronous USART |
| 01 | Synchronous USART |
| 10 | Reserved |
| 11 | Master SPI (MSPIM)(1) |
- The UDORD, UCPHA, and UCPOL can be set in the same write operation where the MSPIM is enabled.
Bits 5:4 – UPMn[1:0] USART Parity Mode
These bits enable and set the type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM setting. If a mismatch is detected, the UPE Flag in UCSRnA will be set.
| UPM[1:0] | ParityMode |
|---|---|
| 00 | Disabled |
| 01 | Reserved |
| 10 | Enabled, Even Parity |
| 11 | Enabled, Odd Parity |
These bits are reserved in Master SPI Mode (MSPIM).
Bit 3 – USBSn USART Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter n. The Receiver ignores this setting.
| USBS | Stop Bit(s) |
|---|---|
| 0 | 1-bit |
| 1 | 2-bit |
This bit is reserved in Master SPI Mode (MSPIM).
Bit 2 – UCSZn1 / UDORDn USART Character Size / Data Order
UCSZ1[1:0]: USART Modes: The UCSZ1[1:0] bits combined with the UCSZ12 bit in UCSR1B sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use.
| UCSZ1[2:0] | Character Size |
|---|---|
| 000 | 5-bit |
| 001 | 6-bit |
| 010 | 7-bit |
| 011 | 8-bit |
| 100 | Reserved |
| 101 | Reserved |
| 110 | Reserved |
| 111 | 9-bit |
UDORD0: Master SPI Mode: When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the USART in SPI Mode - Frame Formats for details.
Bit 1 – UCSZn0 / UCPHAn USART Character Size / Clock Phase
UCSZ0: USART Modes: Refer to UCSZ1.
UCPHA: Master SPI Mode: The UCPHA bit setting determine if data is sampled on the leading edge (first) or tailing (last) edge of XCK. Refer to the SPI Data Modes and Timing for details.
Bit 0 – UCPOLn Clock Polarity
USART n Modes: This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn).
| UCPOL | Transmitted Data Changed (Output of TxDn Pin) | Received Data Sampled (Input on RxDn Pin) |
|---|---|---|
| 0 | Rising XCKn Edge | Falling XCKn Edge |
| 1 | Falling XCKn Edge | Rising XCKn Edge |
Master SPI Mode: The UCPOL bit sets the polarity of the XCKn clock. The combination of the UCPOL and UCPHA bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing for details.