2.8.1 MDDR Subsystem

The MDDR subsystem has two interfaces to the DDR: An AXI 64-bit bus from the DDR bridge within the HPMS and a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize most of the internal registers within the MDDR subsystem after reset. This APB configuration bus is mastered by a host in the FPGA fabric. Support for 3.3V single data-rate DRAMs (SDRAM) can be obtained by instantiating a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connecting I/O ports to 3.3V MSIO.