2.8 High-Speed Memory Interfaces: DDRx Memory Controllers

There are up to two DDR subsystems, MDDR (HPMS DDR), and FDDR (fabric DDR) present in IGLOO 2 devices. Each subsystem consists of a DDR controller, PHY, and a wrapper. The MDDR has an interface to/from the HPMS and fabric, and FDDR provides an interface to/from the fabric.

The following list contains the main features supported by the FDDR and MDDR:

• Supports LPDDR, DDR2, and DDR3 memories
• Simplified DDR command interface to standard AMBA AXI/AHB interface
• Up to 667 Mbps (333 MHz double data-rate) performance
• Supports 1, 2, or 4 ranks of memory
• Supports different DRAM bus width modes: ×8, ×9, ×16, ×18, ×32, and ×36
• Supports DRAM burst length of 2, 4, or 8 in full bus-width mode; supports DRAM burst length of 2, 4, 8, or 16 in Half bus-Width mode
• Supports memory densities up to 4 GB
• Supports a maximum of eight memory banks
• SECDED enable/disable feature
• PHY
• Read and write buffers in fully associative CAMs, configurable in powers of 2, up to 64 reads plus 64 writes
• Supports dynamically changing clock frequency while in self-refresh
• Supports command reordering to optimize memory efficiency
• Supports data reordering, returning critical word first for each command