2.5 High-Performance Memory Subsystem

The High-Performance Memory Subsystem (HPMS) embeds two separate 32 KB SRAM blocks that have optional SECDED capabilities (32 KB with SECDED enabled, 40 KB with SECDED disabled), up to two separate 256 KB eNVM (Flash) blocks, and two separate DMA controllers for fast DMA user logic offloading. The HPMS provides multiple interfacing options to the FPGA fabric to facilitate tight integration between the HPMS and user logic in the fabric.