13.3 External Interrupts

The External Interrupts are triggered by the INT0 pins or any of the PCINT[11:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI0 will trigger if any enabled PCINT[11:0] pin toggles. The Pin Change Mask 0/1 Register (PCMSK 0/1) controls which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A (EICRA). When the INT0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in Clock Systems and their Distribution chapter.