13.4.6 Pin Change Mask Register 0

Name: PCMSK0
Offset: 0x0F
Reset: 0x00
Property: -

Bit 76543210 
 PCINTn[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – PCINTn[7:0] Pin Change Enable Mask [n = 7:0]

Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.