13.4.1 External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.
Name: EICRA
Offset: 0x15
Reset: 0x00
Property: -

Bit 76543210 
       ISC0[1:0] 
Access R/WR/W 
Reset 00 

Bits 1:0 – ISC0[1:0] Interrupt Sense Control 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
ValueDescription
00 The low level of INT0 generates an interrupt request.
01 Any logical change on INT0 generates an interrupt request.
10 The falling edge of INT0 generates an interrupt request.
11 The rising edge of INT0 generates an interrupt request.