22.4.3.4 Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages.

The following are lock sequence:

  1. Execute the ‘Set Lock Bit’ command by writing the EEFC_FCR.FCMD bit with the SLB command and EEFC_FCR.FARG with a page number to be protected.
  2. When the locking completes, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
  3. The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command.
    Note: The value of the FARG argument passed together with SLB command must not exceed the higher lock bit index available in the product.

The following two errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
  • Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or programmed. The unlock sequence is the following:

  1. Execute the ‘Clear Lock Bit’ command by writing the EEFC_FCR.FCMD bit with the CLB command and the EEFC_FCR.FARG bit with a page number to be unprotected.
  2. When the unlock completes, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the interrupt line of the interrupt controller is activated.
    Note: The value of the FARG argument passed together with CLB command must not exceed the higher lock bit index available in the product.

Two errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
  • Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following:

  1. Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Field EEFC_FCR.FARG is meaningless.
  2. Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR return 0.

For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked.

Two errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.

  • Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

    Note: Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed.