22.4.3.2 Write Commands

DMA write accesses must be 32-bit aligned. If a single byte has to be written in a 32-bit word, the rest of the word must be written with ones.

Several commands are used to program the Flash.

Only ‘0’ values can be programmed using Flash technology; ‘1’ is the erased value. In order to program words in a page, the page must first be erased. Commands are available to erase the entire Flash or a given number of pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming.

After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands.

Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space.

Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported.

32-bit words must be written continuously in either ascending or descending order. Writing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order.

Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash.

The latch buffer is automatically re-initialized, that is, written with logical ‘1’, after execution of each programming command.

The programming sequence is as follows:

  1. Write the data to be programmed in the latch buffer.
  2. Write the programming command in EEFC_FCR. This automatically clears the EEFC_FSR.FRDY bit.
  3. When Flash programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the interrupt line of the EEFC is activated.

Three errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
  • Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.
  • Flash Error: When programming is completed, the WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming).

Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash.

When a ‘Write Page’ (WP) command is issued, the EEFC starts the programming sequence and all the bits written at ‘0’ in the latch buffer are cleared in the Flash memory array.

During programming, that is, until EEFC_FSR.FDRY rises, access to the Flash is not allowed.