22.4.3.5 GPNVM Bit

The GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the “Memories” chapter.

The ‘Set GPNVM Bit’ sequence is the following:

  1. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set.
  2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
  3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command.
Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8.

Two errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
  • Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following:

  1. Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be cleared.
  2. When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8.

Two errors can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
  • Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set high.

The status of GPNVM bits can be returned by the EEFC. The sequence is the following:

  1. Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field EEFC_FCR.FARG is meaningless.
  2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to EEFC_FRR return 0.

For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active.

One error can be detected in EEFC_FSR after a programming sequence:

  • Command Error: A bad keyword has been written in EEFC_FCR.
Note: Access to the Flash in read is permitted when a ‘Set GPNVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is executed.