16.7.2 Debug Architecture

Figure 16-4 shows the debug architecture used. The Cortex-M7 embeds six functional units for debug:

  • Serial Wire Debug Port (SW-DP) debug access
  • FPB (Flash Patch Breakpoint)
  • DWT (Data Watchpoint and Trace)
  • ITM (Instrumentation Trace Macrocell)
  • 6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface Unit (TPIU)
  • IEEE1149.1 JTAG Boundary scan on all digital pins

The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and debugging tool vendors for Cortex-M7-based microcontrollers. For further details on SW-DP, see the Cortex - M7 Technical Reference Manual.

Figure 16-4. Debug Architecture