42.7.3.4 Host Receiver Mode

Host Receiver mode is not available if High-speed mode is selected.

The read sequence begins by setting the START bit. After the START condition has been sent, the Host sends a 7-bit Client address to notify the Client device. The bit following the Client address indicates the transfer direction, 1 in this case (MREAD = 1 in TWIHS_MMR). During the acknowledge clock pulse (9th pulse), the Host releases the data line (HIGH), enabling the Client to pull it down in order to generate the acknowledge. The Host polls the data line during this clock pulse and sets TWIHS_SR.NACK if the Client does not acknowledge the byte.

If an acknowledge is received, the Host is then ready to receive data from the Client. After data has been received, the Host sends an acknowledge condition to notify the Client that the data has been received except for the last data (see Host Read with One Data Byte). When TWIHS_SR.RXRDY is set, a character has been received in the Receive Holding register (TWIHS_RHR). The RXRDY bit is reset when reading the TWIHS_RHR.

When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Host Read with One Data Byte. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received (same condition applies for START bit to generate a REPEATED START). See Host Read with Multiple Data Bytes. For internal address usage, see Internal Address.

If TWIHS_RHR is full (RXRDY high) and the Host is receiving data, the serial clock line is tied low before receiving the last bit of the data and until the TWIHS_RHR is read. Once the TWIHS_RHR is read, the Host stops stretching the serial clock line and ends the data reception. See Host Read Clock Stretching with Multiple Data Bytes.

Warning: When receiving multiple bytes in Host Read mode, if the next-to-last access is not read (the RXRDY flag remains high), the last access is not completed until TWIHS_RHR is read. The last access stops on the next-to-last bit (clock stretching). When the TWIHS_RHR is read, there is only half a bit period to send the STOP (or START) command, else another read access might occur (spurious access).

A possible workaround is to set the STOP (or START) bit before reading the TWIHS_RHR on the next-to-last access (within IT handler).

Figure 42-7. Host Read with One Data Byte

Figure 42-8. Host Read with Multiple Data Bytes

Figure 42-9. Host Read Clock Stretching with Multiple Data Bytes

RXRDY is used as receive ready for the DMA receive channel.