31.18.1 Host Clock Switching Timings
The following two tables, Clock Switching Timings (Worst Case) and Clock Switching Timings Between Two PLLs (Worst Case) give the worst case timings required for MCK to switch from one selected clock to another one. This is in the event that the prescaler is deactivated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added.
| From | MAINCK | SLCK | PLL Clock | |
|---|---|---|---|---|
| To | ||||
| MAINCK | – | 4 x SLCK + 2.5 x MAINCK | 3 x PLL Clock + 4 x SLCK + 1 x MAINCK | |
| SLCK | 0.5 x MAINCK + 4.5 x SLCK | – | 3 x PLL Clock + 5 x SLCK | |
| PLL Clock | 0.5 x MAINCK + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLL Clock | 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK | See the following table. | |
Note:
- PLL designates any available PLL of the Clock Generator.
- PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
| From | PLLACK | UPLL Clock | |
|---|---|---|---|
| To | |||
| PLLACK | – | 3 x PLLACK + 4 x SLCK + 1.5 x PLLACK | |
| UPLLCKDIV | 3 x UPLLCKDIV + 4 x SLCK + 1.5 x UPLLCKDIV | – |