43.9 Register Summary

Note: Offsets 0x100–0x128 are reserved for PDC registers.
OffsetNameBit Pos.76543210
0x00SSC_CR7:0      RXDISRXEN
15:8SWRST     TXDISTXEN
23:16        
31:24        
0x04SSC_CMR7:0DIV[7:0]
15:8    DIV[11:8]
23:16        
31:24        

0x08

...

0x0F

Reserved         
0x10SSC_RCMR7:0CKG[1:0]CKICKO[2:0]CKS[1:0]
15:8   STOPSTART[3:0]
23:16STTDLY[7:0]
31:24PERIOD[7:0]
0x14SSC_RFMR7:0MSBF LOOPDATLEN[4:0]
15:8    DATNB[3:0]
23:16 FSOS[2:0]FSLEN[3:0]
31:24FSLEN_EXT[3:0]   FSEDGE
0x18SSC_TCMR7:0CKG[1:0]CKICKO[2:0]CKS[1:0]
15:8    START[3:0]
23:16STTDLY[7:0]
31:24PERIOD[7:0]
0x1CSSC_TFMR7:0MSBF DATDEFDATLEN[4:0]
15:8    DATNB[3:0]
23:16FSDENFSOS[2:0]FSLEN[3:0]
31:24FSLEN_EXT[3:0]   FSEDGE
0x20SSC_RHR7:0RDAT[7:0]
15:8RDAT[15:8]
23:16RDAT[23:16]
31:24RDAT[31:24]
0x24SSC_THR7:0TDAT[7:0]
15:8TDAT[15:8]
23:16TDAT[23:16]
31:24TDAT[31:24]

0x28

...

0x2F

Reserved         
0x30SSC_RSHR7:0RSDAT[7:0]
15:8RSDAT[15:8]
23:16        
31:24        
0x34SSC_TSHR7:0TSDAT[7:0]
15:8TSDAT[15:8]
23:16        
31:24        
0x38SSC_RC0R7:0CP0[7:0]
15:8CP0[15:8]
23:16        
31:24        
0x3CSSC_RC1R7:0CP1[7:0]
15:8CP1[15:8]
23:16        
31:24        
0x40SSC_SR7:0  OVRUNRXRDY  TXEMPTYTXRDY
15:8    RXSYNTXSYNCP1CP0
23:16      RXENTXEN
31:24        
0x44SSC_IER7:0  OVRUNRXRDY  TXEMPTYTXRDY
15:8    RXSYNTXSYNCP1CP0
23:16        
31:24        
0x48SSC_IDR7:0  OVRUNRXRDY  TXEMPTYTXRDY
15:8    RXSYNTXSYNCP1CP0
23:16        
31:24        
0x4CSSC_IMR7:0  OVRUNRXRDY  TXEMPTYTXRDY
15:8    RXSYNTXSYNCP1CP0
23:16        
31:24        

0x50

...

0xE3

Reserved         
0xE4SSC_WPMR7:0       WPEN
15:8WPKEY[7:0]
23:16WPKEY[15:8]
31:24WPKEY[23:16]
0xE8SSC_WPSR7:0       WPVS
15:8WPVSRC[7:0]
23:16WPVSRC[15:8]
31:24