50.6.2.1 Channel Block Diagram

Figure 50-3. Functional View of the Channel Block Diagram

Each of the 4 channels is composed of six blocks:

A clock selector which selects one of the clocks provided by the clock generator (described in PWM Clock Generator ).
A counter clocked by the output of the clock selector. This counter is incremented or decremented according to the channel configuration and comparators matches. The size of the counter is 16 bits.
A comparator used to compute the OCx output waveform according to the counter value and the configuration. The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx bit in the PWM Sync Channels Mode Register (PWM_SCM).
A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.
A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external power control switches safely.
An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx).
An asynchronous fault protection mechanism that has the highest priority to override the two complementary outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to ‘0’, ‘1’ or Hi-Z).