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50.7.15 PWM Interrupt Disable Register 2 Name: PWM_IDR2 Offset: 0x38 Reset: – Property: Write-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 Access W W W W W W W W Reset 0 0 0 0 0 0 0 –
Bit 15 14 13 12 11 10 9 8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 Access W W W W W W W W Reset 0 0 0 0 0 0 0 –
Bit 7 6 5 4 3 2 1 0 UNRE WRDY Access W W Reset – –
Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update Interrupt Disable
Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx Comparison x Match Interrupt Disable
Bit 3 – UNRE Synchronous Channels Update Underrun Error Interrupt Disable
Bit 0 – WRDY Write Ready for Synchronous Channels Update Interrupt Disable
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Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update Interrupt Disable Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx Comparison x Match Interrupt Disable Bit 3 – UNRE Synchronous Channels Update Underrun Error Interrupt Disable Bit 0 – WRDY Write Ready for Synchronous Channels Update Interrupt Disable
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