19.2.3 Host to Client Access

The following table provides valid paths for Host to Client accesses. The paths shown as “-” are forbidden or not wired.

Table 19-3. Host to Client Access
Hosts 0 1 2 3 4 5 6 7 8 9 10 11 12
Clients Cortex-M7 Cortex-M7 Cortex-M7 Peripheral Port ICM Central DMA IF0 Central DMA IF1 ISI DMA

MediaLB DMA

USB DMA

GMAC DMA

CAN0 DMA

CAN1 DMA

Cortex-M7
0 Internal SRAM X X
1 Internal SRAM X X

X

X

X

X

X

2 Internal ROM X
3 Internal Flash X X X X

X

4 USB HS
Dual Port RAM X
5 External Bus Interface X X X X X

X

X

X

X

X

6 QSPI X X X

X

X
7 Peripheral Bridge X X X
8 Cortex-M7 AHB Client (AHBS) (see Note) X X X

X

X

X

X

X

Note: For the connection of the Cortex-M7 processor to the SRAM, refer to the sections “Interconnect” and “Memories”, sub-section “Embedded Memories”.