19.4 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	MATRIX_MCFG0	7:0						ULBT[2:0]
		15:8
		23:16
		31:24
...
0x30	MATRIX_MCFG12	7:0						ULBT[2:0]
		15:8
		23:16
		31:24
0x34 ... 0x3F	Reserved
0x40	MATRIX_SCFG0	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x44	MATRIX_SCFG1	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x48	MATRIX_SCFG2	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x4C	MATRIX_SCFG3	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x50	MATRIX_SCFG4	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x54	MATRIX_SCFG5	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x58	MATRIX_SCFG6	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x5C	MATRIX_SCFG7	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x60	MATRIX_SCFG8	7:0	SLOT_CYCLE[6:0]
		15:8							SLOT_CYCLE[8:7]
		23:16			FIXED_DEFMSTR[3:0]				DEFMSTR_TYPE[1:0]
		31:24
0x64 ... 0x7F	Reserved
0x80	MATRIX_PRAS0	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0x84	MATRIX_PRBS0	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0x88	MATRIX_PRAS1	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0x8C	MATRIX_PRBS1	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0x90	MATRIX_PRAS2	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0x94	MATRIX_PRBS2	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0x98	MATRIX_PRAS3	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0x9C	MATRIX_PRBS3	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xA0	MATRIX_PRAS4	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0xA4	MATRIX_PRBS4	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xA8	MATRIX_PRAS5	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0xAC	MATRIX_PRBS5	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xB0	MATRIX_PRAS6	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0xB4	MATRIX_PRBS6	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xB8	MATRIX_PRAS7	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0xBC	MATRIX_PRBS7	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xC0	MATRIX_PRAS8	7:0			M1PR[1:0]				M0PR[1:0]
		15:8			M3PR[1:0]				M2PR[1:0]
		23:16			M5PR[1:0]				M4PR[1:0]
		31:24			M7PR[1:0]				M6PR[1:0]
0xC4	MATRIX_PRBS8	7:0			M9PR[1:0]				M8PR[1:0]
		15:8			M11PR[1:0]				M10PR[1:0]
		23:16							M12PR[1:0]
		31:24
0xC8 ... 0xFF	Reserved
0x0100	MATRIX_MRCR	7:0	RCB7	RCB6	RCB5	RCB4	RCB3	RCB2	RCB1	RCB0
		15:8				RCB12	RCB11	RCB10	RCB9	RCB8
		23:16
		31:24
0x0104 ... 0x010F	Reserved
0x0110	CCFG_CAN0	7:0	Reserved[7:0]
		15:8								Reserved[8]
		23:16	CAN0DMABA[7:0]
		31:24	CAN0DMABA[15:8]
0x0114	CCFG_SYSIO	7:0	SYSIO7	SYSIO6	SYSIO5	SYSIO4
		15:8				SYSIO12
		23:16	CAN1DMABA[7:0]
		31:24	CAN1DMABA[15:8]
0x0118	CCFG_PCCR	7:0
		15:8
		23:16		I2SC1CC	I2SC0CC	TC0CC
		31:24
0x011C	CCFG_DYNCKG	7:0						EFCCKG	BRIDCKG	MATCKG
		15:8
		23:16
		31:24
0x0120 ... 0x0123	Reserved
0x0124	CCFG_SMCNFCS	7:0					SMC_NFCS3	SMC_NFCS2	SMC_NFCS1	SMC_NFCS0
		15:8
		23:16
		31:24
0x0128 ... 0x01E3	Reserved
0x01E4	MATRIX_WPMR	7:0								WPEN
		15:8	WPKEY[7:0]
		23:16	WPKEY[15:8]
		31:24	WPKEY[23:16]
0x01E8	MATRIX_WPSR	7:0								WPVS
		15:8	WPVSRC[7:0]
		23:16	WPVSRC[15:8]
		31:24