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15.13.14 PIE4
Peripheral Interrupt Enable Register 4| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | TMR6IE | TMR5IE | TMR4IE | TMR3IE | TMR2IE | TMR1IE | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 5 – TMR6IE TMR6 to PR6 Match Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 4 – TMR5IE TMR5 Overflow Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 3 – TMR4IE TMR4 to PR4 Match Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 2 – TMR3IE TMR3 Overflow Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 1 – TMR2IE TMR2 to PR2 Match Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 0 – TMR1IE TMR1 Overflow Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
