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15.13.13 PIE3
Peripheral Interrupt Enable Register 3| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RC1IE | TX1IE | | | BCL1IE | SSP1IE | |
| Access | | | R/W | R/W | | | R/W | R/W | |
| Reset | | | 0 | 0 | | | 0 | 0 | |
Bit 5 – RCxIE EUSARTx Receive Interrupt Enable bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 4 – TXxIE EUSARTx Transmit Interrupt Enable bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 1 – BCLxIE MSSPx Bus Collision Interrupt Enable bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
Bit 0 – SSPxIE Synchronous Serial Port ‘x’ Interrupt Enable
bit
| Value | Description |
|---|
| 1 |
Enabled |
| 0 |
Disabled |
