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15.13.22 IPR4
Peripheral Interrupt Priority Register 4| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | TMR6IP | TMR5IP | TMR4IP | TMR3IP | TMR2IP | TMR1IP | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 5 – TMR6IP TMR6 to PR6 Match Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 4 – TMR5IP TMR5 Overflow Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 3 – TMR4IP TMR4 to PR4 Match Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 2 – TMR3IP TMR3 Overflow Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 1 – TMR2IP TMR2 to PR2 Match Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
Bit 0 – TMR1IP TMR1 Overflow Interrupt Priority
bit
| Value | Description |
|---|
| 1 |
High
priority |
| 0 |
Low
priority |
