2.3 Clocking Structure

The following figure shows the clocking structure of the demo design.

Figure 2-4. Clocking Structur
As shown in the preceding figure, the on-board 50 MHz crystal oscillator provides a reference clock to the PF_CCC_C0 block. PF_CCC_C0 generates the following clocks:
  • 200 MHz clock that drives all the blocks of top_0 and PFSOC_DSP_FLOW_TOP
  • 25 MHz slow clock is a secondary clock needed by the CoreFFT block which is within the PFSOC_DSP_FLOW_TOP