2.5 Simulating the Design

A testbench (top.v) is provided to simulate the design. The testbench simulates the filter pattern and waveform selection. It contains the test selection for the coefficient inputs (low-pass, high-pass, band-pass, and band-stop) and data input. It also monitors the UART_IF module status signals, output signals (DATAOUT), and FFT output status signals (DATA Valid and output ready) for the verification of filter output.

The following figure shows the simulation waveform.

Figure 2-6. CoreFIR Input and Output Signals
Important: To get this waveform, perform the following steps:
  1. Change the radix of the input to decimal, right-click DATAI, go to the radix option, and select decimal.
  2. Right-click DATAI, select the format option and select Analog (automatic).

In the preceding figure:

  • COEFFI represents Input coefficients
  • DATAI represents FIR input data
  • FIRO represents FIR output data

The following figure contains the Low-Pass Filter Output waveform, which is highlighted in the following figure.

Figure 2-7. Low-Pass Filter Output

In the preceding figure:

  • DATAO_IM represents the imaginary part of the FFT output
  • DATAO_RE represents the real part of the FFT output