2.1 Design Implementation

This section shows the DSP Filter design implemented using the CoreFIR and CoreFFT IP cores in Libero SoC.

The following figure shows the top-level SmartDesign, which includes the clocking (PF_CCC_C0_0), Reset (CORERESET_PF_C0_0), the SmartDesign of DSP Flow (PFSOC_DSP_FLOW_TOP), and COREUART_C0_0.

Figure 2-2. Top-level SmartDesign

The following figure shows the PFSOC_DSP_FLOW_TOP SmartDesign, which includes FIR filter (COREFIR_PF_C0_0), FFT filter (COREFFT_PF_C0_0), buffers, control FSM and UART_IF blocks.

Figure 2-3. DSP FIR Filter SmartDesign

For more information on creating the demo design using Tcl, see Appendix 1: Running the Tcl Script.

Important: There is a known issue with the CoreFIR IP due to which the FIR output valid signal (FIRO_VALID) is not used; instead, an initial latency of 128 cycles is used as a workaround. This will be fixed in the next release.

This reference design and the associated GUI are created to support only the given CoreFIR and CoreFFT IP configurations.