32.10.5 Device Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x14
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
       LPMSUSPLPMNYET 
Access R/WR/W 
Reset 00 
Bit 76543210 
 RAMACERUPRSMEORSMWAKEUPEORSTSOFMSOFSUSPEND 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Link Power Management Suspend interrupt is disabled.
1 The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the Link Power Management Suspend interrupt Flag is set.

Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Link Power Management Not Yet interrupt is disabled.
1 The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated when the Link Power Management Not Yet interrupt Flag is set.

Bit 7 – RAMACER RAM Access Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The RAM Access interrupt is disabled.
1 The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt Flag is set.

Bit 6 – UPRSM Upstream Resume Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Upstream Resume interrupt is disabled.
1 The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set.

Bit 5 – EORSM End Of Resume Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The End Of Resume interrupt is disabled.
1 The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume interrupt Flag is set.

Bit 4 – WAKEUP Wake-Up Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Wake Up interrupt is disabled.
1 The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is set.

Bit 3 – EORST End of Reset Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The End of Reset interrupt is disabled.
1 The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt Flag is set.

Bit 2 – SOF Start-of-Frame Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Start-of-Frame interrupt is disabled.
1 The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame interrupt Flag is set.

Bit 1 – MSOF Micro Start-of-Frame Interrupt Enable in High Speed Mode

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Micro Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Micro Start-of-Frame interrupt is disabled.
1 The Micro Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Micro Start-of-Frame Access interrupt Flag is set.

Bit 0 – SUSPEND Suspend Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Suspend interrupt is disabled.
1 The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set.