32.10.1 Control B

Name: CTRLB
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
     LPMHDSK[1:0]GNAKOPMODE2 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 TSTPCKTTSTKTSTJNREPLYSPDCONF[1:0]UPRSMDETACH 
Access R/WR/WR/WRR/WR/WR/WR/W 
Reset 00000000 

Bits 11:10 – LPMHDSK[1:0] Link Power Management Handshake

These bits select the Link Power Management Handshake configuration.

ValueDescription
0x0 No handshake. LPM is not supported.
0x1 ACK
0x2 NYET
0x3 Reserved

Bit 9 – GNAK Global NAK

This bit configures the operating mode of the NAK.

This bit is not synchronized.

ValueDescription
0 The handshake packet reports the status of the USB transaction
1 A NAK handshake is answered for each USB transaction regardless of the current endpoint memory bank status

Bit 8 – OPMODE2 Specific Operational Mode

ValueDescription
0 The UTMI transceiver is in normal operation Mode.
1 The UTMI transceiver is in the “disabled bit stuffing and NRZI encoding” operational mode for test purpose.

Bit 7 – TSTPCKT Test Packet Mode

ValueDescription
0 The UTMI transceiver is in normal operation Mode.
1 The UTMI transceiver generates test packets for test purpose.

Bit 6 – TSTK Test Mode K

ValueDescription
0 The UTMI transceiver is in normal operation Mode.
1 The UTMI transceiver generates high speed K state for test purpose.

Bit 5 – TSTJ Test Mode J

ValueDescription
0 The UTMI transceiver is in normal operation Mode.
1 The UTMI transceiver generates high speed J state for test purpose.

Bit 4 – NREPLY No reply excepted SETUP Token

This bit is cleared by hardware when receiving a SETUP packet.

This bit has no effect for any other endpoint but endpoint 0.

ValueDescription
0 Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the USB2.0 standard.
1 Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP.

Bits 3:2 – SPDCONF[1:0] Speed Configuration

These bits select the speed configuration.

ValueDescription
0x0 FS: Full-speed
0x1 LS: Low-speed
0x2 HS: High-speed capable
0x3 HSTM: High-speed Test Mode (force High-speed mode for test mode)

Bit 1 – UPRSM Upstream Resume

This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.

ValueDescription
0 Writing a zero to this bit has no effect.
1 Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.

Bit 0 – DETACH Detach

ValueDescription
0 The device is attached to the USB bus so that communications may occur.
1 It is the default value at reset. The internal device pull-ups are disabled, removing the device from the USB bus.