40.6 Maximum Clock Frequencies
| Symbol | Description | Conditions | Max | Units |
|---|---|---|---|---|
| fGCLKGEN0 / fGCLK_MAIN | GCLK Generator Output Frequency | Undivided | 64 | MHz |
| fGCLKGEN1 | Divided | 32 | MHz | |
| fGCLKGEN2 | ||||
| fGCLKGEN3 | ||||
| fGCLKGEN4 | ||||
| fGCLKGEN5 |
| Symbol | Description | Max. | Units |
|---|---|---|---|
| fCPU | CPU clock frequency | 32 | MHz |
| fAHB | AHB clock frequency | 32 | MHz |
| fAPBA | APBA clock frequency | 32 | MHz |
| fAPBB | APBB clock frequency | 32 | MHz |
| fAPBC | APBC clock frequency | 32 | MHz |
| fGCLK_DFLL48M_REF | DFLL48M Reference clock frequency | 33 | kHz |
| fGCLK_DPLL | FDPLL96M Reference clock frequency | 2 | MHz |
| fGCLK_DPLL_32K | FDPLL96M 32k Reference clock frequency | 32 | kHz |
| fGCLK_WDT | WDT input clock frequency | 48 | MHz |
| fGCLK_RTC | RTC input clock frequency | 48 | MHz |
| fGCLK_EIC | EIC input clock frequency | 48 | MHz |
| fGCLK_USB | USB input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_0 | EVSYS channel 0 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_1 | EVSYS channel 1 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_2 | EVSYS channel 2 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_3 | EVSYS channel 3 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_4 | EVSYS channel 4 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_5 | EVSYS channel 5 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_6 | EVSYS channel 6 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_7 | EVSYS channel 7 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_8 | EVSYS channel 8 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_9 | EVSYS channel 9 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_10 | EVSYS channel 10 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_11 | EVSYS channel 11 input clock frequency | 48 | MHz |
| fGCLK_SERCOMx_SLOW | Common SERCOM slow input clock frequency | 48 | MHz |
| fGCLK_SERCOM0_CORE | SERCOM0 input clock frequency | 48 | MHz |
| fGCLK_SERCOM1_CORE | SERCOM1 input clock frequency | 48 | MHz |
| fGCLK_SERCOM2_CORE | SERCOM2 input clock frequency | 48 | MHz |
| fGCLK_SERCOM3_CORE | SERCOM3 input clock frequency | 48 | MHz |
| fGCLK_SERCOM4_CORE | SERCOM4 input clock frequency | 48 | MHz |
| fGCLK_SERCOM5_CORE | SERCOM5 input clock frequency | 48 | MHz |
| fGCLK_TCC0, fGCLK_TCC1 | TCC0, TCC1 input clock frequency | 80 | MHz |
| fGCLK_TCC2, fGCLK_TC3 | TCC2,TC3 input clock frequency | 80 | MHz |
| fGCLK_TC4, fGCLK_TC5 | TC4, TC5 input clock frequency | 48 | MHz |
| fGCLK_TC6, fGCLK_TC7 | TC6,TC7 input clock frequency | 48 | MHz |
| fGCLK_ADC | ADC input clock frequency | 48 | MHz |
| fGCLK_AC_DIG | AC digital input clock frequency | 48 | MHz |
| fGCLK_AC_ANA | AC analog input clock frequency | 64 | kHz |
| fGCLK_DAC | DAC input clock frequency | 48 | MHz |
| fGCLK_PTC | PTC input clock frequency | 48 | MHz |
| fGCLK_I2S_0 | I2S serial 0 input clock frequency | 13 | MHz |
| fGCLK_I2S_1 | I2S serial 1 input clock frequency | 13 | MHz |
| Symbol | Description | Conditions | Max | Units |
|---|---|---|---|---|
| fGCLKGEN0 / fGCLK_MAIN | GCLK Generator Output Frequency | Undivided | 96 | MHz |
| fGCLKGEN1 | Divided | 48 | MHz | |
| fGCLKGEN2 | ||||
| fGCLKGEN3 | ||||
| fGCLKGEN4 | ||||
| fGCLKGEN5 |
| Symbol | Description | Max. | Units |
|---|---|---|---|
| fCPU | CPU clock frequency | 48 | MHz |
| fAHB | AHB clock frequency | 48 | MHz |
| fAPBA | APBA clock frequency | 48 | MHz |
| fAPBB | APBB clock frequency | 48 | MHz |
| fAPBC | APBC clock frequency | 48 | MHz |
| fGCLK_DFLL48M_REF | DFLL48M Reference clock frequency | 33 | KHz |
| fGCLK_DPLL | FDPLL96M Reference clock frequency | 2 | MHz |
| fGCLK_DPLL_32K | FDPLL96M 32k Reference clock frequency | 32 | KHz |
| fGCLK_WDT | WDT input clock frequency | 48 | MHz |
| fGCLK_RTC | RTC input clock frequency | 48 | MHz |
| fGCLK_EIC | EIC input clock frequency | 48 | MHz |
| fGCLK_USB | USB input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_0 | EVSYS channel 0 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_1 | EVSYS channel 1 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_2 | EVSYS channel 2 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_3 | EVSYS channel 3 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_4 | EVSYS channel 4 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_5 | EVSYS channel 5 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_6 | EVSYS channel 6 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_7 | EVSYS channel 7 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_8 | EVSYS channel 8 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_9 | EVSYS channel 9 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_10 | EVSYS channel 10 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_11 | EVSYS channel 11 input clock frequency | 48 | MHz |
| fGCLK_SERCOMx_SLOW | Common SERCOM slow input clock frequency | 48 | MHz |
| fGCLK_SERCOM0_CORE | SERCOM0 input clock frequency | 48 | MHz |
| fGCLK_SERCOM1_CORE | SERCOM1 input clock frequency | 48 | MHz |
| fGCLK_SERCOM2_CORE | SERCOM2 input clock frequency | 48 | MHz |
| fGCLK_SERCOM3_CORE | SERCOM3 input clock frequency | 48 | MHz |
| fGCLK_SERCOM4_CORE | SERCOM4 input clock frequency | 48 | MHz |
| fGCLK_SERCOM5_CORE | SERCOM5 input clock frequency | 48 | MHz |
| fGCLK_TCC0, GCLK_TCC1 | TCC0, TCC1 input clock frequency | 96 | MHz |
| fGCLK_TCC2,fGCLK_TCC3, GCLK_TC3 | TCC2, TCC3, TC3 input clock frequency | 96 | MHz |
| fGCLK_TC4, GCLK_TC5 | TC4, TC5 input clock frequency | 48 | MHz |
| fGCLK_TC6, GCLK_TC7 | TC6,TC7 input clock frequency | 48 | MHz |
| fGCLK_ADC | ADC input clock frequency | 48 | MHz |
| fGCLK_AC_DIG | AC digital input clock frequency | 48 | MHz |
| fGCLK_AC_ANA | AC analog input clock frequency | 64 | kHz |
| fGCLK_DAC | DAC input clock frequency | 48 | MHz |
| fGCLK_PTC | PTC input clock frequency | 48 | MHz |
| fGCLK_I2S_0 | I2S serial 0 input clock frequency | 13 | MHz |
| fGCLK_I2S_1 | I2S serial 1 input clock frequency | 13 | MHz |