3.2.4.1 PIOA Bank
The PIOA bank is mainly used for the FLEXCOM4, NAND and part of GMAC0 interfaces over power rails VDDIOP0, VDDSDMMC0 and VDDGMAC0, respectively.
The following schematic shows the PIOA bank distribution.
The following table describes each PIOA bank function.
| PIO | Power Rail | Function | Signal Description |
|---|---|---|---|
|
PA0 |
VDDSDMMC0 |
NAND_WE |
NAND Flash Write Enable signal |
|
PA1 |
VDDSDMMC0 |
NAND_ALE |
NAND Flash Address Latch Enable signal |
|
PA2 |
VDDSDMMC0 |
NAND_CLE |
NAND Flash Command Latch Enable signal |
|
PA3 |
VDDSDMMC0 |
NAND_D0 |
NAND Flash data 0 |
|
PA4 |
VDDSDMMC0 |
NAND_D1 |
NAND Flash data 1 |
|
PA5 |
VDDSDMMC0 |
NAND_D4 |
NAND Flash data 4 |
|
PA6 |
VDDSDMMC0 |
NAND_D5 |
NAND Flash data 5 |
|
PA7 |
VDDSDMMC0 |
NAND_D6 |
NAND Flash data 6 |
|
PA8 |
VDDSDMMC0 |
NAND_D7 |
NAND Flash data 7 |
|
PA9 |
VDDSDMMC0 |
NAND_D2 |
NAND Flash data 2 |
|
PA10 |
VDDSDMMC0 |
NAND_D3 |
NAND Flash data 3 |
|
PA11 |
VDDSDMMC0 |
NAND_RDY |
NAND Flash Ready signal |
|
PA12 |
VDDSDMMC0 |
NAND_RE |
NAND Flash Output Enable signal |
|
PA13 |
VDDSDMMC0 |
NAND_CS |
NAND Flash Chip Select line |
|
PA14 |
VDDIOP0 |
FLEXCOM4_IO4 |
mikroBUS2 Chip Select |
|
PA15 |
VDDIOP0 |
FLEXCOM4_IO3 |
mikroBUS1 Chip Select |
|
PA16 |
VDDIOP0 |
FLEXCOM4_IO2 |
SPI clock (RPi, mikroBUS1, mikroBUS2) |
|
PA17 |
VDDIOP0 |
FLEXCOM4_IO1 |
SPI MISO (RPi, mikroBUS1, mikroBUS2) |
|
PA18 |
VDDIOP0 |
FLEXCOM4_IO0 |
SPI MOSI (RPi, mikroBUS1, mikroBUS2) |
|
PA19 |
VDDIOP0 |
FLEXCOM4_IO5 |
RPi SPI Chip Select 0 |
|
PA20 |
VDDIOP0 |
FLEXCOM4_IO6 |
RPi SPI Chip Select 1/GMAC1 SPI Chip Select |
|
PA21 |
VDDIOP0 |
LED_BLUE |
RGB LED blue channel |
|
PA22 |
VDDIOP0 |
MBUS2_INT |
mikroBUS2 interrupt |
|
PA23 |
VDDIOP0 |
RPi_RXD |
RPi UART RX |
|
PA24 |
VDDIOP0 |
RPi_TXD |
RPi UART TX |
|
PA25 |
VDDGMAC0 |
GMAC0_TXCTL |
GMAC0 RGMII transmit enable |
|
PA26 |
VDDGMAC0 |
GMAC0_TX0 |
GMAC0 RGMII transmit data 0 |
|
PA27 |
VDDGMAC0 |
GMAC0_TX1 |
GMAC0 RGMII transmit data 1 |
|
PA28 |
VDDGMAC0 |
GMAC0_RXCTL |
GMAC0 RGMII Receive Control signal |
|
PA29 |
VDDGMAC0 |
GMAC0_RX0 |
GMAC0 RGMII RX data line 0 |
|
PA30 |
VDDGMAC0 |
GMAC0_RX1 |
GMAC0 RGMII RX data line 1 |
|
PA31 |
VDDGMAC0 |
GMAC0_MDC |
GMAC0 Management Data Clock signal |