3.2.4.4 PIOD Bank
The PIOD bank is mainly used for CAN and GMAC1 RGMII interfaces, over power rails VDDSDMMC2, VDDIOP1 and VDDGMAC1. The following schematic shows the PIOD bank distribution.
The following table describes each PIOD bank function.
| PIO | Power Rail | Function | Signal Description |
|---|---|---|---|
|
PD0 |
VDDSDMMC2 |
SDMMC2_DAT3 |
M.2 SDMMC2 DAT3 signal |
|
PD1 |
VDDIOP1 |
PD1 PIO |
M.2 interrupt line/RPI GPIO22 signal (not connected by default, R123 DNP) |
|
PD2 |
VDDIOP1 |
PD2 PIO |
M.2 TWI interrupt line/RPI GPIO23 signal (not connected by default, R125 DNP) |
|
PD3 |
VDDIOP1 |
BT_RTS |
M.2 UART RTS signal |
|
PD4 |
VDDIOP1 |
WIFI_WAKE_HOST |
M.2 WiFi interrupt line |
|
PD5 |
VDDIOP1 |
BT_CTS |
M.2 UART CTS signal |
|
PD6 |
VDDIOP1 |
BT_RXD |
M.2 UART RX signal |
|
PD7 |
VDDIOP1 |
BT_TXD |
M.2 UART TX signal |
|
PD8 |
VDDIOP1 |
MBUS1_TX/CAN0_TX |
mikroBUS1 TX signal/CAN0 TX signal |
|
PD9 |
VDDIOP1 |
MBUS1_RX/CAN0_RX |
mikroBUS1 RX signal/CAN0 RX signal |
|
PD10 |
VDDIOP1 |
CAN1_TX |
CAN1 TX signal |
|
PD11 |
VDDIOP1 |
CAN1_RX |
CAN1 RX signal |
|
PD12 |
VDDIOP1 |
CAN2_TX |
CAN2 TX signal |
|
PD13 |
VDDIOP1 |
CAN2_RX |
CAN2 RX signal |
|
PD14 |
VDDIOP1 |
CAN3_TX |
CAN3 TX signal |
|
PD15 |
VDDIOP1 |
CAN3_RX |
CAN3 RX signal |
|
PD16 |
VDDIOP1 |
MBUS2_TX/CAN4_TX |
mikroBUS2 TX signal/CAN4 TX signal |
|
PD17 |
VDDIOP1 |
MBUS2_RX/CAN4_RX |
mikroBUS2 RX signal/CAN4 RX signal |
|
PD18 |
VDDGMAC1 |
DBGU_TX |
MPU UART debug TX |
|
PD19 |
VDDGMAC1 |
DBGU_RX |
MPU UART debug RX |
|
PD20 |
VDDGMAC1 |
PD20 PIO |
M.2 reset line/RPI GPCLK1 signal (not connected by default, R127 DNP) |
|
PD21 |
VDDGMAC1 |
GMAC1_TXEN |
GMAC1 RGMII Transmit Enable signal |
|
PD22 |
VDDGMAC1 |
GMAC1_TX0 |
GMAC1 RGMII TX data line 0 |
|
PD23 |
VDDGMAC1 |
GMAC1_TX1 |
GMAC1 RGMII TX data line 1 |
|
PD24 |
VDDGMAC1 |
GMAC1_RXCTL |
GMAC1 RGMII Receive Control signal |
|
PD25 |
VDDGMAC1 |
GMAC1_MDC |
GMAC1 RGMII management data clock |
|
PD26 |
VDDGMAC1 |
GMAC1_MDIO |
GMAC1 RGMII Management Data I/O signal |
|
PD27 |
VDDGMAC1 |
GMAC1_RX0 |
GMAC1 RGMII RX data line 0 |
|
PD28 |
VDDGMAC1 |
GMAC1_RX1 |
GMAC1 RGMII RX data line 1 |
|
PD29 |
VDDGMAC1 |
GMAC1_TXCK |
GMAC1 RGMII transmit clock |
|
PD30 |
VDDGMAC1 |
GMAC1_RX2 |
GMAC1 RGMII RX data line 2 |
|
PD31 |
VDDGMAC1 |
GMAC1_RX3 |
GMAC1 RGMII RX data line 3 |