3.2.4.5 PIOE Bank

The PIOE bank is mainly used for GMAC1 and LVDS interfaces, over VDDGMAC1 and VDDLVDS power rails. The following schematic shows the PIOE bank distribution.

Figure 3-20. SAMA7D6 Series PIOE Bank Distribution

The following table describes each PIOE bank function.

Table 3-7. SAMA7D6 Series PIOE Bank Pin Assignment and Signal Description
PIO	Power Rail	Function	Signal Description
PE0	VDDGMAC1	GMAC1_TX2	GMAC1 RGMII TX data line 2
PE1	VDDGMAC1	GMAC1_TX3	GMAC1 RGMII TX data line 3
PE2	VDDGMAC1	GMAC1_RXCK	GMAC1 RGMII Receive Clock signal
PE3	VDDGMAC1	GMAC1_IRQ	GMAC1 Interrupt signal
PE4	VDDLVDS	LCD_LVDS_DO_N	LCD LVDS Data Lane 0 Negative signal
PE5	VDDLVDS	LCD_LVDS_DO_P	LCD LVDS Data Lane 0 Positive signal
PE6	VDDLVDS	LCD_LVDS_D1_N	LCD LVDS Data Lane 1 Negative signal
PE7	VDDLVDS	LCD_LVDS_D1_P	LCD LVDS Data Lane 1 Positive signal
PE8	VDDLVDS	LCD_LVDS_D2_N	LCD LVDS Data Lane 2 Negative signal
PE9	VDDLVDS	LCD_LVDS_D2_P	LCD LVDS Data Lane 2 Positive signal
PE10	VDDLVDS	LCD_LVDS_D3_N	LCD LVDS Data Lane 3 Negative signal
PE11	VDDLVDS	LCD_LVDS_D3_P	LCD LVDS Data Lane 3 Positive signal
PE12	VDDLVDS	LCD_LVDS_CK_N	LCD LVDS Clock Negative signal
PE13	VDDLVDS	LCD_LVDS_CK_P	LCD LVDS Clock Positive signal